Blog post from Philippe Gastaldo, Product and R&D Director, UnitySC.
As the automotive electronics market continues to grow, spurred by developments such as semi-autonomous and fully autonomous vehicles, the demand is increasing for power semiconductor components with sophisticated conversion schemes that decrease power consumption and heat. To address these needs, power semiconductor manufacturers are turning to thin wafers.
Today’s power semiconductors are manufactured primarily on 200-mm wafers that range in thickness from 50 to 100 µm, but their roadmaps are targeting wafers as thin as 1 µm. These wafers are thinned on the backside by mechanical polishing. Defects resulting from the polishing process include grinding marks, grinding failures resulting in edge chips, star cracks and comets formed by edge particles that get caught in the grinding wheel, embedded particles, cleavage lines, and a variety of other imperfections [Evaluation Engineering].
Article published by UnitySC in Chip Scale Review (July-Aug 2017, Volume 21, Number 4)
With the increase of costs, delays and complexity at the most advanced frontend silicon technology nodes, advanced packaging process control solutions have become a key differentiator for achieving next-generation requirements, and thereby continued sustainability in the semiconductor industry. Within the advanced packaging realm, fan-out wafer level packaging (FOWLP) is gaining momentum due to its high integration, extreme flexibility, performance enablement and cost advantages, compared with more conventional assembly technologies.
Despite the wide adoption of FOWLP during the last few years, there are several challenges remaining about the industrialization of the process. For example, regardless of the FOWLP methodology used, the epoxy molding compound (EMC) is still a potential source of issues, with challenges in total thickness variation (TTV) management, package warpage and die shift. From a pure metrology perspective, the EMC thickness measurement may also be a challenge, because the epoxy material typically becomes opaque above a certain thickness and cannot be measured in the visible or infrared domains by conventional optical metrology techniques.
In this article, we introduce the various metrology technologies used to control the FOWLP process and review the main metrology measurements required during high-volume manufacturing. Additionally, we explore the advantages of using an inline, integrated 2D/3D metrology solution to characterize the FOWLP fabrication process using the chip-first/face-down approach.
Gilles Fresquet, CEO, and Yann Guillou, Global Marketing Manager, mentionned in the article written by Francoise von Trapp from 3DInCites
In the first part of this series, I covered the perspectives of dimensional scaling vs. heterogeneous integration based on discussions during SEMICON West 2017. For part two, I spoke with equipment and material suppliers who serve either (or in some cases, both) the front- and back-ends of the semiconductor manufacturing industry, to round out the picture of how the industry-wide shift in focus from scaling to the heterogeneous integration roadmap is impacting them [3DInCites].
Event dates: October 24, 2017 - October 26, 2017
San Jose, CA
Wafer Level Packaging is almost everywhere: smartphones, automotive, IoT, medtech, etc…
Meet with us at IWLPC on booth #10 and listen to our talk entitled “Wafer Thinning In-Line Inspection Process Control Solution for High Volume Manufacturing”. To pre-arrange a meeting, send us a message.
Event dates: October 9, 2017 - October 12, 2017
UnitySC will be exhibiting on booth #421 and delivering a talk entitled “In line Advanced Process Control Solution for the Fabrication of Micro-bumps”. Come to meet with us. To pre-arrange a meeting, send us a message.
Event dates: September 20, 2017 - September 22, 2017
3rd edition of the SEMI MEMS and Sensor Summit will take place in Grenoble from Sept 20th to 22nd. Looking for versatile process control solutions compliant with high volume manufacturing ? Stop by our booth #21 to learn about our TMap Series and 4See Series. To pre-arranged a meeting, send us a message.
Event dates: September 13, 2017 - September 15, 2017
Taipei Nangang Exhibition Center, Taiwan
Taiwan is a key region for UnitySC with many customers and tools installed. From Sept 13 to 15th, we will be co-exhibiting with our local representative, Kingyoup Entreprises. Visit us on booth #930, 4th floor, and learn more about our innovative product lines. To pre-arrange a meeting at the show, send us a message.
June 28, 2017
Most would agree that in order for advanced packaging solutions to lead the industry and fill the role previously held by semiconductor scaling it must see advances in infrastructure building and significant focus by all players to lower costs. For sure, this will take total industry unity. With this cheap play on words we are led to todays topic… A few blogs ago (see IFTLE 332: “Wither Goest the Toshiba NAND business; Unity SC”) we mentioned that Fogale’s semiconductor division had become UnitySC. This week, we’d like to take a closer look at what this means to the advanced packaging industry [Solid State Technology].
June 19, 2017
Gilles Fresquet, CEO of UnitySC, mentionned in the article written by Francoise von Trapp from 3DInCites.
[…] UnitySC filled me in on their most recent inspection platform targeting heterogeneous integration, the 4See Series, an all-surface wafer inspection system designed as a completed solution for 2D and 3D optical and edge inspection. According to Unity’s Gilles Fresquet, it’s the only inspection platform that can be configured to inspect all around and through the wafer. The platform features a deflector module that uses phase shift deflectometry for wafer surface inspection, an edge and line-scan modules that rely on confocal chromatic technology […] [3DInCites]