Event dates: December 5, 2017 - December 7, 2017
San Francisco, USA
Gilles Fresquet, CEO UnitySC, will deliver an invited talk entitled “TSV, FOWLP, Hybrid Bonding : Review of Metrology Challenges and Solutions to Support HVM”. Check the event website for more information.
Article published in Silicon Semiconductor (Volume 39, Issue 4 2017)
Thin and ultrathin ICs are in high demand, but yield that sacrifices reliability has little value. Inspection process control can be the solution, according to UnitySC. By Gilles Fresquet, CEO, UnitySC. Read the full article in page 40.
November 9, 2017
Francoise von Trapp (3D Incites) refers to UnitySC’s latest announcement in her coverage of IWLPC.
After reading the announcement of UnitySC’s opening of its new software development lab and customer support demo lab, I caught up with the Philippe Gastaldo, Product and R&D Director, UnitySC, at IWLPC, who filled me in on the details. […]
October 23, 2017
New Facility Enhances Company’s Semiconductor Process Control Capabilities and Supports Growing North America Customer Base
Austin, Texas – Oct. 23, 2017 – UnitySC today announced at the International Wafer Level Packaging Conference (IWLPC) in San Jose, Calif., the opening of Unity Semiconductor Inc., the company’s new global software development center and North America customer demonstration lab located in Austin, Texas. The new facility serves as the company’s main center for software development, and will house the full line of UnitySC metrology and inspection tools. This equipment will provide a demo lab that supports UnitySC’s North America customer base, augmenting the primary demo lab at the company’s global headquarters, located in Grenoble, France.
Blog post from Philippe Gastaldo, Product and R&D Director, UnitySC.
As the automotive electronics market continues to grow, spurred by developments such as semi-autonomous and fully autonomous vehicles, the demand is increasing for power semiconductor components with sophisticated conversion schemes that decrease power consumption and heat. To address these needs, power semiconductor manufacturers are turning to thin wafers.
Today’s power semiconductors are manufactured primarily on 200-mm wafers that range in thickness from 50 to 100 µm, but their roadmaps are targeting wafers as thin as 1 µm. These wafers are thinned on the backside by mechanical polishing. Defects resulting from the polishing process include grinding marks, grinding failures resulting in edge chips, star cracks and comets formed by edge particles that get caught in the grinding wheel, embedded particles, cleavage lines, and a variety of other imperfections [Evaluation Engineering].
Article published by UnitySC in Chip Scale Review (July-Aug 2017, Volume 21, Number 4)
With the increase of costs, delays and complexity at the most advanced frontend silicon technology nodes, advanced packaging process control solutions have become a key differentiator for achieving next-generation requirements, and thereby continued sustainability in the semiconductor industry. Within the advanced packaging realm, fan-out wafer level packaging (FOWLP) is gaining momentum due to its high integration, extreme flexibility, performance enablement and cost advantages, compared with more conventional assembly technologies.
Despite the wide adoption of FOWLP during the last few years, there are several challenges remaining about the industrialization of the process. For example, regardless of the FOWLP methodology used, the epoxy molding compound (EMC) is still a potential source of issues, with challenges in total thickness variation (TTV) management, package warpage and die shift. From a pure metrology perspective, the EMC thickness measurement may also be a challenge, because the epoxy material typically becomes opaque above a certain thickness and cannot be measured in the visible or infrared domains by conventional optical metrology techniques.
In this article, we introduce the various metrology technologies used to control the FOWLP process and review the main metrology measurements required during high-volume manufacturing. Additionally, we explore the advantages of using an inline, integrated 2D/3D metrology solution to characterize the FOWLP fabrication process using the chip-first/face-down approach.
Gilles Fresquet, CEO, and Yann Guillou, Global Marketing Manager, mentionned in the article written by Francoise von Trapp from 3DInCites
In the first part of this series, I covered the perspectives of dimensional scaling vs. heterogeneous integration based on discussions during SEMICON West 2017. For part two, I spoke with equipment and material suppliers who serve either (or in some cases, both) the front- and back-ends of the semiconductor manufacturing industry, to round out the picture of how the industry-wide shift in focus from scaling to the heterogeneous integration roadmap is impacting them [3DInCites].
Event dates: October 24, 2017 - October 26, 2017
San Jose, CA
Wafer Level Packaging is almost everywhere: smartphones, automotive, IoT, medtech, etc…
Meet with us at IWLPC on booth #10 and listen to our talk entitled “Wafer Thinning In-Line Inspection Process Control Solution for High Volume Manufacturing”. To pre-arrange a meeting, send us a message.