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Francoise von Trapp (3D Incites) refers to UnitySC’s latest announcement in her coverage of IWLPC.

After reading the announcement of UnitySC’s opening of its new software development lab and customer support demo lab, I caught up with the Philippe Gastaldo, Product and R&D Director, UnitySC, at IWLPC, who filled me in on the details. […]

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New Facility Enhances Company’s Semiconductor Process Control Capabilities and Supports Growing North America Customer Base

Austin, Texas – Oct. 23, 2017UnitySC today announced at the International Wafer Level Packaging Conference (IWLPC) in San Jose, Calif., the opening of Unity Semiconductor Inc., the company’s new global software development center and North America customer demonstration lab located in Austin, Texas. The new facility serves as the company’s main center for software development, and will house the full line of UnitySC metrology and inspection tools. This equipment will provide a demo lab that supports UnitySC’s North America customer base, augmenting the primary demo lab at the company’s global headquarters, located in Grenoble, France.

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Blog post from Philippe Gastaldo,  Product and R&D Director, UnitySC.

As the automotive electronics market continues to grow, spurred by developments such as semi-autonomous and fully autonomous vehicles, the demand is increasing for power semiconductor components with sophisticated conversion schemes that decrease power consumption and heat. To address these needs, power semiconductor manufacturers are turning to thin wafers.

Today’s power semiconductors are manufactured primarily on 200-mm wafers that range in thickness from 50 to 100 µm, but their roadmaps are targeting wafers as thin as 1 µm. These wafers are thinned on the backside by mechanical polishing. Defects resulting from the polishing process include grinding marks, grinding failures resulting in edge chips, star cracks and comets formed by edge particles that get caught in the grinding wheel, embedded particles, cleavage lines, and a variety of other imperfections [Evaluation Engineering].

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Article published by UnitySC in Chip Scale Review (July-Aug 2017, Volume 21, Number 4)

With the increase of costs, delays and complexity at the most advanced frontend silicon technology nodes, advanced packaging process control solutions have become a key differentiator for achieving next-generation requirements, and thereby continued sustainability in the semiconductor industry. Within the advanced packaging realm, fan-out wafer level packaging (FOWLP) is gaining momentum due to its high integration, extreme flexibility, performance enablement and cost advantages, compared with more conventional assembly technologies.

Despite the wide adoption of FOWLP during the last few years, there are several challenges remaining about the industrialization of the process. For example, regardless of the FOWLP methodology used, the epoxy molding compound (EMC) is still a potential source of issues, with challenges in total thickness variation (TTV) management, package warpage and die shift. From a pure metrology perspective, the EMC thickness measurement may also be a challenge, because the epoxy material typically becomes opaque above a certain thickness and cannot be measured in the visible or infrared domains by conventional optical metrology techniques.

In this article, we introduce the various metrology technologies used to control the FOWLP process and review the main metrology measurements required during high-volume manufacturing. Additionally, we explore the advantages of using an inline, integrated 2D/3D metrology solution to characterize the FOWLP fabrication process using the chip-first/face-down approach.

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Gilles Fresquet, CEO, and Yann Guillou, Global Marketing Manager, mentionned in the article written by Francoise von Trapp from 3DInCites

In the first part of this series, I covered the perspectives of dimensional scaling vs. heterogeneous integration based on discussions during SEMICON West 2017. For part two, I spoke with equipment and material suppliers who serve either (or in some cases, both) the front- and back-ends of the semiconductor manufacturing industry, to round out the picture of how the industry-wide shift in focus from scaling to the heterogeneous integration roadmap is impacting them [3DInCites].

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Most would agree that in order for advanced packaging solutions to lead the industry and fill the role previously held by semiconductor scaling it must see advances in infrastructure building and significant focus by all players to lower costs. For sure, this will take total industry unity. With this cheap play on words we are led to todays topic… A few blogs ago (see IFTLE 332: “Wither Goest the Toshiba NAND business; Unity SC”) we mentioned that Fogale’s semiconductor division had become UnitySC. This week, we’d like to take a closer look at what this means to the advanced packaging industry [Solid State Technology].

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Gilles Fresquet, CEO of UnitySC, mentionned in the article written by Francoise von Trapp from 3DInCites.
[…] UnitySC filled me in on their most recent inspection platform targeting heterogeneous integration, the 4See Series, an all-surface wafer inspection system designed as a completed solution for 2D and 3D optical and edge inspection. According to Unity’s Gilles Fresquet, it’s the only inspection platform that can be configured to inspect all around and through the wafer. The platform features a deflector module that uses phase shift deflectometry for wafer surface inspection, an edge and line-scan modules that rely on confocal chromatic technology […] [3DInCites]

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Gilles Fresquet, CEO of UnitySC, mentionned in the article written by Francoise von Trapp from 3DInCites.

The fan-out conversation that started at IMAPS DPC 2017 in March continued this week at the annual Electronics Components Technology Conference (ECTC), which took place in Orlando at the Walt Disney World Swan and Dolphin Resort. The buzz started during the Tuesday evening plenary session, where panelists Douglas Yu, TSMC, Tim Olson, Deca Technologies; Steffen Kroehnert, NANIUM; Rolf Aschenbrenner, Fraunhofer IZM; and Steve Bezuk, Qualcomm Technologies, Inc. discussed the why, how and when of panel-level fan out (PLFO) [3DIncites].

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What is expected from inspection and metrology equipment, and how will it evolve in the future?

Advanced packaging has grown into a complex ecosystem with a variety of business models and a series of players involved, from initial wafer processing steps to final package delivery and subsequent board assembly. The spotlight has turned to advanced packaging as one of the solutions to bring further value to the semiconductor product in terms of cost reduction and functionality increase […]. Our lead analysts for the areas of equipment and materials sat down with UnitySC CEO Gilles Fresquet and Global Marketing Manager Yann Guillou to discuss the trends in advanced packaging and their impact on inspection and metrology tools [I-Micronews].

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Advanced packaging is now mainstream, but making sure these devices work properly while also cutting costs is getting harder. As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, 2.5D and 3D-IC, along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moore’s Law. [Semiconductor Engineering]

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UnitySC delivers visionary technologies that foster progress for people. We are recognized as a key player in inspection and metrology combining advanced technologies to enable higher yields and faster time to market.

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