phone
+33 (0)456 526 800

T-MAP 3D

Time-domain Optical Coherence is the most robust solution for TSV depth, bow & warp and individual layer TTV of a stack measurement as each interface is detected in the right order over a larger range than spectral interferometry. The only limitation is the minimum measurable thickness due to the high coherence length of the IR LED source.

Read More

Article published in Silicon Semiconductor (Volume 39, Issue 4 2017)

Thin and ultrathin ICs are in high demand, but yield that sacrifices reliability has little value. Inspection process control can be the solution, according to UnitySC. By Gilles Fresquet, CEO, UnitySC. Read the full article in page 40.

有人已经考虑将暗视野检测用于检测薄晶圆缺陷。基于光学技术,暗视野是指进行较低角度反射光测量。 暗视野对于晶圆前端检测是有效的,但是由于研磨造成晶圆背面粗糙,对于背面检测它是无效的。因此,晶圆背面研磨后应避免暗视野检测。

Read more

Francoise von Trapp (3D Incites) refers to UnitySC’s latest announcement in her coverage of IWLPC.

After reading the announcement of UnitySC’s opening of its new software development lab and customer support demo lab, I caught up with the Philippe Gastaldo, Product and R&D Director, UnitySC, at IWLPC, who filled me in on the details. […]

Read more

Blog post from Philippe Gastaldo,  Product and R&D Director, UnitySC.

As the automotive electronics market continues to grow, spurred by developments such as semi-autonomous and fully autonomous vehicles, the demand is increasing for power semiconductor components with sophisticated conversion schemes that decrease power consumption and heat. To address these needs, power semiconductor manufacturers are turning to thin wafers.

Today’s power semiconductors are manufactured primarily on 200-mm wafers that range in thickness from 50 to 100 µm, but their roadmaps are targeting wafers as thin as 1 µm. These wafers are thinned on the backside by mechanical polishing. Defects resulting from the polishing process include grinding marks, grinding failures resulting in edge chips, star cracks and comets formed by edge particles that get caught in the grinding wheel, embedded particles, cleavage lines, and a variety of other imperfections [Evaluation Engineering].

Read more

Article published by UnitySC in Chip Scale Review (July-Aug 2017, Volume 21, Number 4)

With the increase of costs, delays and complexity at the most advanced frontend silicon technology nodes, advanced packaging process control solutions have become a key differentiator for achieving next-generation requirements, and thereby continued sustainability in the semiconductor industry. Within the advanced packaging realm, fan-out wafer level packaging (FOWLP) is gaining momentum due to its high integration, extreme flexibility, performance enablement and cost advantages, compared with more conventional assembly technologies.

Despite the wide adoption of FOWLP during the last few years, there are several challenges remaining about the industrialization of the process. For example, regardless of the FOWLP methodology used, the epoxy molding compound (EMC) is still a potential source of issues, with challenges in total thickness variation (TTV) management, package warpage and die shift. From a pure metrology perspective, the EMC thickness measurement may also be a challenge, because the epoxy material typically becomes opaque above a certain thickness and cannot be measured in the visible or infrared domains by conventional optical metrology techniques.

In this article, we introduce the various metrology technologies used to control the FOWLP process and review the main metrology measurements required during high-volume manufacturing. Additionally, we explore the advantages of using an inline, integrated 2D/3D metrology solution to characterize the FOWLP fabrication process using the chip-first/face-down approach.

Read more

Gilles Fresquet, CEO, and Yann Guillou, Global Marketing Manager, mentionned in the article written by Francoise von Trapp from 3DInCites

In the first part of this series, I covered the perspectives of dimensional scaling vs. heterogeneous integration based on discussions during SEMICON West 2017. For part two, I spoke with equipment and material suppliers who serve either (or in some cases, both) the front- and back-ends of the semiconductor manufacturing industry, to round out the picture of how the industry-wide shift in focus from scaling to the heterogeneous integration roadmap is impacting them [3DInCites].

Read more

Most would agree that in order for advanced packaging solutions to lead the industry and fill the role previously held by semiconductor scaling it must see advances in infrastructure building and significant focus by all players to lower costs. For sure, this will take total industry unity. With this cheap play on words we are led to todays topic… A few blogs ago (see IFTLE 332: “Wither Goest the Toshiba NAND business; Unity SC”) we mentioned that Fogale’s semiconductor division had become UnitySC. This week, we’d like to take a closer look at what this means to the advanced packaging industry [Solid State Technology].

Read more

Gilles Fresquet, CEO of UnitySC, mentionned in the article written by Francoise von Trapp from 3DInCites.
[…] UnitySC filled me in on their most recent inspection platform targeting heterogeneous integration, the 4See Series, an all-surface wafer inspection system designed as a completed solution for 2D and 3D optical and edge inspection. According to Unity’s Gilles Fresquet, it’s the only inspection platform that can be configured to inspect all around and through the wafer. The platform features a deflector module that uses phase shift deflectometry for wafer surface inspection, an edge and line-scan modules that rely on confocal chromatic technology […] [3DInCites]

Read more

Gilles Fresquet, CEO of UnitySC, mentionned in the article written by Francoise von Trapp from 3DInCites.

The fan-out conversation that started at IMAPS DPC 2017 in March continued this week at the annual Electronics Components Technology Conference (ECTC), which took place in Orlando at the Walt Disney World Swan and Dolphin Resort. The buzz started during the Tuesday evening plenary session, where panelists Douglas Yu, TSMC, Tim Olson, Deca Technologies; Steffen Kroehnert, NANIUM; Rolf Aschenbrenner, Fraunhofer IZM; and Steve Bezuk, Qualcomm Technologies, Inc. discussed the why, how and when of panel-level fan out (PLFO) [3DIncites].

Read more

 

UnitySC delivers visionary technologies that foster progress for people. We are recognized as a key player in inspection and metrology combining advanced technologies to enable higher yields and faster time to market.

phone
+33 (0)456 526 800