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Bridging the IC / PCB interconnect gap

Driven by cell phones requirements such as lower footprint, thinner, and higher performance packaging solutions, wafer level technologies took off in the mid 2000’s. Limited to Fan-In Wafer Level Packaging (FIWLP) at the beginning, wafer level packaging technologies expanded to Fan-Out Wafer Level Packaging (FOWLP) in the late 2010’s. Main principle of the FOWLP is to expand the FIWLP application space by embedding the silicon die in epoxy mold compound to enlarge it, redistribute the signals, and allowing to fit all I/O under the rebuilt structure. Similarly, to FIWLP, FOWLP does not require laminate substrates to attach the silicon die to the main PCB. FOWLP is a disruptive approach compared to previously used packaging platforms. Performed at wafer level with some processes similar to front end fabs, it requires new type of equipment to solve new challenges. Metrology solutions from UnitySC were developed to support foundries, OSAT and IDMs involved in FOWLP.

 

UNITYSC’S SOLUTION: TMAP SERIES

TMap Series is a single metrology solution that can be used from molding process start to interconnect completion. It provides accurate measurements even under warped condition and non-homogeneous mold compound materials. Key measurements performed by TMAP Series for FOWLP includes various thickness measurements of individual layers (EMC, PR, PI, glue, carrier) and total stack, TTV, bow, warp, roughness, CD.

TMAP Series has unique thickness metrology capability for die first face up FOWLP approach.

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UnitySC delivers visionary technologies that foster progress for people. We are recognized as a key player in inspection and metrology combining advanced technologies to enable higher yields and faster time to market.

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+33 (0)456 526 800